This application is related to and claims priority from Korean Application No. 2000-72091, filed Nov. 30, 2000, the disclosure of which is hereby incorporated herein by reference.
The present invention relates to integrated circuit devices and fabrication methods, and more particularly, to integrated circuit devices having trench isolation structures that include a conductive plug that is electrically connected to the substrate and related fabrication methods.
Improved active device isolation techniques may be desirable in order to facilitate ongoing attempts to increase integration density in integrated circuit devices by designing devices having reduced unit cell size. Conventional device isolation techniques include local oxidation of silicon (LOCOS) and shallow trench isolation (STI) techniques, for example. Such device isolation techniques are disclosed in U.S. Pat. Nos. 6,187,651, 6,218,273, 6,251,746, 5,885,883, 5,940,716, 6,001,696 and 6,037,237.
Such techniques may, however, exhibit problems that may affect the reliability of the integrated circuit. For example, the LOCOS technique, when applied to highly integrated devices, may exhibit oxide thinning and punch through parasitics. Moreover, LOCOS techniques tend to produce devices having narrow width effect. In other words, as width of the channel of an integrated circuit is reduced, the threshold voltage of the channel may increase.
By way of further example, STI techniques that include the formation of trench isolation regions, also may exhibit problems that may affect the reliability of the integrated circuit. First, a parasitic xe2x80x9chumpxe2x80x9d phenomenon may occur. The hump phenomenon means that the turn-on characteristics of a transistor formed in the active region may be deteriorated because of the presence of a parasitic transistor (adjacent the sidewall portions of the active region) having a relatively low threshold voltage. Second, an inverse narrow-width effect is generated. The inverse narrow-width effect is also a parasitic phenomenon, which can, for example, lower the effective threshold voltage as the width of a gate electrode becomes narrower by a strong electric field generated at the sharp edge of the active region. Third, a gate oxide-thinning phenomenon may be generated whereby the gate oxide film formed at the sharp edge portion of the active region is thinner than the gate oxide film formed in another portion removed from the edge portion. This thinner gate oxide film may increase the likelihood of dielectric breakdown, which can deteriorate the characteristics of devices formed in the active region.
Now referring to FIG. 1, a pair of arrows denote an influence of an electric field upon an active region 13 of a specific cell in a conventional Dynamic Random Access Memory (DRAM) device having gate lines 11. FIG. 2 illustrates the effect of cell spacing (Lsp) on the influence of an electric field in a conventional device. As illustrated, the narrower the cell-to-cell spacing, the greater the influence of the electric field. For example, when a voltage VNS applied to a storage node of an adjacent cell is changed from 0V to 2V, a gate voltage VG is 0.5V, and the spacing LSP is 0.1xcexcm, the potential scarcely changes at each position of a conventional channel. On the other hand, if the spacing LSP is 0.06xcexcm, the potential difference may be 0.1V or higher.
To address the issue with respect to the influence of the electric field, insulating layers, for example insulating layer 20 illustrated in FIG. 3, may be filled with a conductive material such as polysilicon 31 to shield the electric field. This technique is discussed in detail in U.S. Pat. No. 6,133,116 to Kim et al. entitled Methods of Forming Trench Isolation Regions Having Conductive Shields Therein, the disclosure of which is hereby incorporated herein by reference in its entirety. Although this approach may improve the existing techniques, it may not completely prevent other causes from lowering the threshold voltage of the device.
Recently, another approach has been suggested, in which impurities may be implanted into a device isolation layer. However, if the implanted impurities are enough to prevent the inverse narrow width effect, a junction profile of a cell may become stiff thus reducing the junction width of the cell, which is also undesirable because an electric field may get concentrated at the junction which may increase a junction leakage current.
Integrated circuit devices according to embodiments of the present invention include an integrated circuit substrate having a face and a trench in the face. The trench has a trench sidewall and a trench floor. A first insulating layer is provided on the trench sidewall that exposes at least part of the trench floor and a conductive plug is provided in the trench on the trench floor. The conductive plug is electrically connected to the substrate at the trench floor through the trench sidewall that exposes the at least part of the trench floor. The conductive plug also has a plug top opposite the trench floor that is recessed beneath the face of the substrate. A second insulating layer is provided on the plug top.
In some embodiments of the present invention the second insulating layer may be on the plug top and extend onto the trench sidewall between the plug top and the face of the substrate. Alternatively, the second insulating layer may be a conformal insulating layer on the plug top that is recessed beneath the face and also extends onto the trench sidewall between the plug top and the face. The first insulating layer may include a first layer of oxide and a second layer of silicon nitride. Alternatively, the first insulating layer may include a layer of SiON. The layer of SiON may have a thickness of from about 10 xc3x85 to about 100 xc3x85.
In further embodiments of the present invention, the conductive plug may include polysilicon. The conductive plug may have a thickness of about 3000 xc3x85. The second insulating layer may include a silicon nitride layer. The silicon nitride layer may have a thickness from about 10 xc3x85 to about 500 xc3x85.
Still further embodiments of the present invention include methods of fabricating integrated circuit devices that include forming a trench in a face of an integrated circuit substrate. The trench has a trench sidewall and a trench floor. The method further including forming a first insulating layer on the trench sidewall that exposes at least part of the trench floor and forming a conductive plug in the trench on the trench floor. The conductive plug is electrically connected to the substrate at the trench floor through the trench sidewall that exposes the at least part of the trench floor. The conductive plug also has a plug top opposite the trench floor that is recessed beneath the face of the substrate. The method further includes forming a second insulating layer on the plug top.